The semiconductor industry's growth and roadmap has historically depended on a reduction in cost per transistor with each new generation of chip technology, as it shrinks to smaller dimensions, but next-generation chips offer less of these cost benefits. Thus, this is one of the major challenges facing the industry over the next decade. This cost problem is derived from difficulties obtaining high parametric yields for devices fabricated on silicon wafers at the new device node sizes.
Many companies across the semiconductor industry are developing 20nm bulk high-K metal gate (HKMG) CMOS as well as 16 to 14nm FinFET logic-based transistors, which have a higher cost per gate than 28nm bulk HKMG CMOS (which is technology I was involved in at ASMI for Intel). However, the node size shrinkage does offer reduced power consumption, which is critical for mobile and/or wearable devices that put a strain on limited battery capacity.
The 20nm node faces difficulty achieving low leakage due to challenges in controlling doping uniformity, line edge device pattern roughness, and other key physical parameters that are very sensitive to minor variations in manufacturing processes. The need for double patterning at 20nm (which is a process flow I helped facilitate and patent at Micron) also adds cost per wafer over 28nm, since it adds a significant number of process steps for manufacturing semiconductor chips compared to past generations of technology, when photolithography capability enabled direct patterning of intended node sizes.
The 16/14nm FinFET node for high-performance computing functionality, uses the same back-end interconnect structure as 20nm, so the chip area is only about nine percent smaller than 20nm node sizes. What’s more, this node has yield complications related to stress-related defects, device pattern layer overlay, and factors related to the high aspect ratio step coverage and process uniformity of 3D structures for aggressive device geometries, requiring the need of atomic layer deposition and etch processes even more. The cost problems are expected to continue as 28nm bulk CMOS technology evolves, while wafer depreciation costs will fall about 60 percent from the ramp-up towards high-volume production.
Therefore, the cost per gate for 28nm bulk HKMG CMOS will be much lower than FinFETs even in the fourth quarter of 2017. However, the emergence of larger 450mm silicon wafers at that time will offer cost-savings benefits through economies of scale. FinFETs are primarily used for high-performance computing applications like processors or low-power designs at smaller node sizes but are not cost-effective in semiconductor chips for lower performance applications.
The semiconductor roadmap includes the scaling to 10nm and 7nm device node sizes, and the jury is still out on which approach will win-out for bringing that technology to fruition including: extreme ultraviolet photolithography (EUV), quadruple patterning, fully-depleted silicon-on-insulator (FD-SOI) layers, carbon nanotubes, and graphene transistors, among others. Worldwide sales of semiconductor manufacturing equipment totaled $31.6 billion in 2013, representing a year-over-year decrease of 14 percent, according to the SEMI industry trade organization, but a nearly equivalent gain on a percentage basis is expected in 2014 to meet future fab technology needs.
The cost of R&D and production for these advanced, lower power consumption chips geared towards mobile devices will likely lead to more consolidation across the industry including the transition towards top foundries such as TSMC, which is already booked through the third quarter of this year. Advanced chips will inevitably be expanded beyond more conventional mobile devices into emerging wearable devices such as Apple’s iWatch to be released this year in order to compete with the Samsung Galaxy Gear smartwatch as well as the recently released Google Glass.
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