The top global microelectronics foundry Taiwan Semiconductor Manufacturing Co. (TSMC) has announced yesterday the release of three reference design flows for FinFET and 3D-stacked ICs for higher performance and lower power consumption processor chips for a wide range of electronics including mobile devices. The validation of these chip manufacturing process flows is a green light for the high-volume production of microchips based on this design scheme following in the footsteps of Intel, which is the originator of this technology. TSMC is reported to have signed to supply Apple with processors for iPhones and iPads on a three-year contract that will include some FinFET production, according to EE Times.
In specific, the three TSMC design include: a digital design flow for TSMC's 16nm FinFET process; a custom design flow for 16nm FinFET that incorporates transistor-level design of analog, digital, mixed-signal, custom digital and memory; and a 3D-IC flow for the design of vertically-stacked structures and multi-die assemblies for chipset packages such as logic-on-memory. EDA software vendors collaborated with TSMC to develop these design schemes using 300mm silicon wafer test vehicles. The 16nm FinFET digital design flow uses the Cortex-A15 multicore processor, licensed from ARM, as its validation vehicle for performance assessment. It facilitates designers in the conversion to FinFET architecture by addressing key device criteria such as: RC modeling, power-performance-area trade-offs, electromigration, and power management. In addition, the flow provides methodologies for boosting power, performance and area (PPA) in 16nm node size devices, including low-voltage operation analysis, and high-resistance layer routing optimization for interconnect resistance minimization.
Integrating multiple components in a single stacked component can offer benefits like physical scaling and power consumption. TSMC's 3D-IC design flow leverages this design via through-transistor-stacking (TTS) technology; through silicon vias (TSVs) plus microbumps, back-side metal routing; and TSV-to-TSV coupling extraction. 3D-IC technology is being developed at nearly all major semiconductor companies globally to boost device performance and lower power consumption of end-user electronic products such as mobile devices.
When it comes to lower power consumption processor chip design schemes, SuVolta is helping revolutionize the industry. Fujitsu Semiconductor began volume production earlier this month of an image processor IC that uses Deeply Depleted Channel (DDC) technology from SuVolta. The DDC technology, which has been licensed from SuVolta by Fujitsu, uses electrically-active doping techniques to form a ground plane under a transistor and represents an alternative way to build low-power logic transistors, in contrast to the fully depleted silicon-on-insulator (FDSOI) and FinFET processes that are being adopted by many top-tier players like Samsung, Intel, GlobalFoundries and TSMC.
SuVolta has shown results that can reduce total power consumption by up to 50 percent, while matching the operating speed of the same IC implemented using conventional transistors at the same planar geometry. Fujitsu was SuVolta's initial development partner and first licensee, and the new MB86S22AA imager IC product is the result of a collaboration that has leveraged less-expensive and highly depreciated 65nm and 55nm manufacturing processes, while meeting initial production, yield, and reliability requirements. Shrinks to 20nm node sizes and beyond are conceivable for this semiconductor technology, which would only boost performance even more. However, this technology is still relatively new and unproven in production, but a successful Fujitsu endeavor would help validate its credentials and boost its adoption for other chips as well.
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