Improved performance, reduced response time and power consumption plus device scaling attributes are key driving forces for the adoption of new microchip technology for mobile devices referred to as 3D integrated circuits (ICs) and through silicon via (TSV) interconnects. Reducing power consumption leads to the benefits of less heat generation, extended battery life, and a lower cost of operation.
TSVs are essentially vertical holes etched or laser drilled into silicon wafers or printed circuit boards and filled with copper or other highly conductive metals, which enable communication between vertically stacked ICs. The technology allows for circuit designers to place stacks of memory chips on top of an application microprocessor or graphics processor chip in order to significantly increase memory bandwidth and reduce power consumption, which are key issues for next-generation mobile devices such as smartphones and tablets. At leading-edge chip node sizes, the adoption of 3D stacking of ICs is increasingly being considered as an alternative to traditional technology node scaling at the transistor level, according to Moore’s Law. TSV technology is leading to major innovations in how chips are packaged, as several thousand could be fabricated on future chips, but trench depth uniformity and repeatability is a concern.
The International Microelectronic Assembly and Packaging Society (IMAPS) held its 9th annual device packaging conference in the Scottsdale, Arizona area recently, which just ended a couple days ago. It featured presentations and exhibits from many of the leaders in advanced microelectronic packaging technology spanning from ICs to MEMS as well as LEDs. The status of TSVs for 3D IC applications such as reduced power consumption was a reoccurring theme throughout the event.
While the drivers for 3D ICs remain performance, form factor and power efficiency, the timeline for its adoption into production continues to be delayed due to technical challenges and a limited infrastructure. Until these issues are resolved, more conventional chip packages will continue to be applied across the industry.
Even though there has been a lot of progress in via formation and filling over the last couple years, there are still several key process steps that significantly impact yield, subsequently plagued with low throughput, such as the debonding step during wafer thinning, which need to be improved. Many companies are developing a silicon interposer solution, where a logic chip is mounted next to a stack of memory devices and the TSVs are formed in the substrate. The problem is that this assumes stacked memory with TSV is commercially available at a cost/performance ratio that matches the requirements, which is not yet the case. Some companies also indicate that the cost of the silicon interposer is too high (up to a ~$1000), and they are considering a lower-cost glass interposer or even a high-density plastic substrate in the meantime.
These new packaging designs have generated an expanding future market opportunity for metrology and defect characterization led by companies such as Rudolph Technologies headquartered in New Jersey, which exhibited at the IMAPS Conference in Arizona. What’s more, a recent report by Research and Markets, cited during the conference, has forecasted that the global 3D IC market will grow at a compound annual growth rate of 19.7 percent until 2016, which was music to the ears of those in attendance and especially the likes of key industry leaders such as ASE Group, TSMC, Samsung and STMicroelectronics.